Method of manufacturing circuit board

ABSTRACT

Disclosed herein is a method of manufacturing a circuit board. The method of manufacturing a circuit board according to a preferred embodiment of the present invention is configured to include (A) forming a cavity  115  for a bump on one surface  111  of a carrier  110,  (B) forming a bump  130  in the cavity  115  for the bump through an electroplating process, (C) laminating an insulating layer  140  on one surface  111  of the carrier  110  so as to apply the bump  130,  (D) forming a circuit layer  150  including a via  155  connected with the bump  130  on the insulating layer  140,  and (E) removing the carrier  110,  whereby the process of forming separate solder balls is removed by forming the cavities  111  for the bumps in the carriers  110  to form the bumps, thereby simplifying the process of manufacturing a circuit board and reducing the lead time.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2010-0109296, filed on Nov. 4, 2010, entitled “Method Of Manufacturing A Circuit Board” which is hereby incorporated by reference in its entirety into this application.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a method of manufacturing a circuit board.

2. Description of the Prior art

Recently, as the development of the electronic industry, a demand for high-performance, multi-functional, and small-sized electronic parts has been increased.

Therefore, a board for surface-mounted parts such as a system in package (SIP), a 3D package, or the like, is becoming a necessity of a high-integrated, thin, and fine circuit pattern.

In particular, in a technology of surface-mounting electronic parts on a board, a wire bonding method and a flip chip bonding method for electrically connecting a semiconductor chip and a printed circuit board has been used.

In this case, the wire bonding method bonds a semiconductor chip on which a design circuit is printed to a printed circuit board by an adhesive, connects a lead frame on the printed circuit board with a metal terminal (that is, pad) of a semiconductor chip by a metal wire for transmitting and receiving information therebetween, and then, molds electronic devices and wires by a thermosetting resin, a thermoplastic resin, or the like.

Since the wire bonding method has higher productivity than other packaging method, but connects the printed circuit board by the wires, a size of a module is increased and an additional process is needed, such that the flip chip bonding method is mainly used in recent.

The flip chip bonding method forms external connection terminals (that is, bump) having a size of several tens of μm to several hundreds of μm on a semiconductor chip by using a material such as gold, solder, other metals, or the like, and mounts a surface of the semiconductor chip on which the bump is formed so as to face a board direction by flipping the semiconductor chip unlike the mounting method according to the existing wire bonding method.

FIG. 1 is a cross-sectional view of a circuit board used for flip chip bonding according to the prior art.

As shown in FIG. 1, a circuit board 10 according to the prior art is configured to include an insulating layer 5 on which a circuit layer 4 including a pad 3 is formed, a solder ball 1 provided on the pad 3 so as to be connected with external devices, and a solder resist layer 2 protecting the circuit layer 4 and including opening that exposes the solder ball 1.

However, a method of manufacturing a circuit board used for the flip chip bonding according to the prior art has the following problems.

First, in order to form the solder ball 1, a process of machining the openings on the solder resist layer 2, a process of printing the solder paste, and a process of reflowing the solder paste need to be performed. Therefore, a process of manufacturing a circuit board may be complicated and thus, much lead time may be consumed.

In addition, since the solder ball 1 is supported only by the pad 3, a bonding strength of the solder ball 1 is weak, such that the solder ball 1 may be destructed or warped by an external force such as a shearing force.

SUMMARY OF THE INVENTION

The present invention has been made in an effort to provide a method of manufacturing a circuit board capable of forming a bump serving as an external connection terminal together with a circuit layer, without performing an additional process.

According to a preferred embodiment of the present invention, there is provided a method of manufacturing a circuit board, including: (A) forming a cavity for a bump on one surface of a carrier; (B) forming a bump in the cavity for the bump through an electroplating process; (C) laminating an insulating layer on one surface of the carrier so as to apply the bump; (D) forming a circuit layer including a via connected with the bump on the insulating layer; and (E) removing the carrier.

At the forming of the cavity for the bump, the cavity for the bump may have a width narrowing in a direction towards the other surface of the carrier. At the forming of the bump, the bump may be protruded from one surface of the carrier.

At the forming of the cavity for the bump, the carrier may be made of metal.

The method of manufacturing a circuit board may further include forming an electroless plating layer on one surface of the carrier by an electroless plating process prior to the forming of the bump.

The method of manufacturing a circuit board may further include removing the electroless plating layer remaining on the insulating layer including the exposed bump after the removing of the carrier.

At the forming of the bump, one surface of the carrier may be provided with a terminal for a passive device, a stiffener, a heat radiation layer, or an electromagnetic wave shield layer by the electroplating process.

At the stacking of the insulating layer, the terminal for the passive device, the stiffener, the heat radiation layer, or the electromagnetic wave shield layer may be embedded in the insulating layer.

At the stacking of the insulating layer, the insulating layer may be a thermosetting insulating layer.

The method of manufacturing a circuit board may further include forming a build up layer on the insulating layer after the forming of the circuit layer on the insulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a circuit board used for flip chip bonding according to the prior art; and

FIGS. 2 to 11 are cross-sectional views showing a method of manufacturing a circuit board according to a preferred embodiment of the present invention in a process order.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various objects, advantages and features of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

The terms and words used in the present specification and claims should not be interpreted as being limited to typical meanings or dictionary definitions, but should be interpreted as having meanings and concepts relevant to the technical scope of the present invention based on the rule according to which an inventor can appropriately define the concept of the term to describe most appropriately the best method he or she knows for carrying out the invention.

The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. In the specification, in adding reference numerals to components throughout the drawings, it is to be noted that like reference numerals designate like components even though components are shown in different drawings. Further, in describing the present invention, a detailed description of related known functions or configurations will be omitted so as not to obscure the gist of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 2 to 11 are cross-sectional views showing a method of manufacturing a circuit board according to a preferred embodiment of the present invention in a process order.

As shown in FIGS. 2 to 11, a method of manufacturing a circuit board 100 according to a preferred embodiment of the present invention is configured to include

(A) forming a cavity 115 for a bump on one surface 111 of a carrier 110, (B) forming a bump 130 in the cavity 115 for the bump through an electroplating process, (C) laminating an insulating layer 140 on one surface 111 of the carrier 110 so as to apply the bump 130, (D) forming a circuit layer 150 including a via 155 connected with the bump 130 on the insulating layer 140, and (E) removing the carrier 110.

First, as shown in FIGS. 2 and 3, the process of preparing the carrier 110 and then, the process of forming the cavity 115 for the bump on one surface 111 of the carrier 110 are performed. In this configuration, the carrier 110 serves to support components of the circuit board during the manufacturing process and may be made of metal such as stainless steel or an organic resin material. When the carrier 110 is made of metal, the carrier 110 serves as a lead-in wire during the electroplating process of the bump 130 to be described below, such that there is no need to form a separate electroless plating layer 120. In addition, when the carrier 110 is made of the organic resin material, desmear processing is performed or the roughenss of the surface is controllded by controlling the hardening degree of the organic resin material, such that the carrier 110 may be easily separated during the final process.

Meanwhile, the cavity 115 for the bump may be machined using laser (YAG laser or CO2 laser), imprint, or drill. In this case, since the shape of the cavity 115 for the bump finally determines the shape of the bump 130, the cavity 115 for the bump is formed in consideration of the necessary shape of the bump 130. Although the shape of the cavity 115 for the bump is not particularly limited, the bump 130 may be manufactured in a ‘V’-letter shape so as to precisely match between the bump 130 and the external device. Therefore, the cavity 115 for the bump may be formed to have a width narrowing in a direction towards the other surface 113 of the carrier 110.

Next, as shown in FIGS. 4 to 6, a process of forming the cavity 130 on the cavity 115 for the bump is performed. In this case, the bump 130 serves as the external connection terminal and is formed by the electroplating process. Therefore, unlike the solder ball according to the prior art, the process of printing the solder paste and the process of reflowing the solder paste, or the like, may be omitted, thereby simplifying the process of manufacturing a circuit board. Describing in detail the present process, it is preferable to form the electroless plating layer 120 on one surface 111 of the carrier 110 through the electroless plating process prior to the electroplating process (see FIG. 4). In this case, the electroless plating layer 120 serves as the lead-in wire during the electroplating process. However, as described above, when the carrier 110 is made of metal, the carrier 110 itself serves as the lead-in wire, such that there is no need to form the electroless plating layer 120.

Thereafter, when the electroplating process is performed, a plating resist 133 may be used so as to selectively form the bump 130 only in the cavity 115 for the bump (see FIG. 5). First, the plating resist 133 is applied to one surface 111 of the carrier 110 and then, an opening 135 corresponding to the cavity 115 for the bump is patterned by an exposure and developing process. Thereafter, the bump 130 is formed by supplying electricity to the electroless plating layer 120 so as to precipitate the electroplating layer from the electroless plating layer 120 within the opening 135. After the bump 130 is formed, the plating resist 133 is removed (see FIG. 6). In this case, the bump 130 is protruded from one surface 111 of the carrier 110 by the thickness of the plating resist 133. A protruding portion 131 of the bump 130 is embedded in the insulating layer 140 that is laminated in the carrier 110 during a process to be described below (see FIG. 7), such that the strong bonding strength between the bump 130 and the circuit board 100 body may be finally implemented.

Meanwhile, when the electroplating process is performed, a terminal 137 for a passive device or a stiffener 139 may be formed by patterning the opening 135 corresponding to the cavity 115 for the bump on the plating resistor 133 and the opening 135 corresponding to the terminal 137 for the passive device and the stiffener 139. In this configuration, the terminal 137 for the passive terminal serves to connect the passive device with the circuit layer 150 and the stiffener 139 serves to prevent the warpage of the board. In this configuration, since one surface of the terminal 137 for the passive device is co-plane with the exposed surface of the insulating layer 140 after the carrier 110 is removed (see FIG. 11), bubbles are not generated when the solder ball, or the like, is printed on the terminal 137 for the passive device, thereby securing the coupling reliability of the terminal 137 for the passive device and the solder ball. Meanwhile, a heat radiation layer radiating heat or an electromagnetic wave shield layer shielding an electromagnetic wave may be formed by patterning the opening 135 on the plating resist 133 using the same method as the method of forming the terminal 137 for the passive device and the stiffener 139.

Next, as shown in FIG. 7, the process of laminating the insulating layer 140 on one surface 111 of the carrier 110 so as to apply the bump 130 is performed. In this configuration, the insulating layer 140 is laminated in a B-stage and thus, the protruding portion 131 of the bump 130 protruded from one surface 111 of the carrier 110, the terminal 137 for the passive device, the stiffener 139, the heat radiation layer, or the electromagnetic wave shield layer is embedded in the insulating layer 140. In addition, when the circuit layer 150 is formed in the insulating layer 140 during the next process, the insulating layer 140 may be the thermosetting insulating layer so as to reinforce the plating adhesion. However, the insulating layer is not necessarily limited to the thermosetting insulating layer and therefore, may use prepreg, ajinomoto build up film (ABF) or FR-4, epoxy-based resin such as bismaleimide triazine (BT), or the like.

Next, as shown in FIGS. 8 to 9A, a process of forming the circuit layer 150 including the via 155 connected to the bump 130 on the insulating layer 140 is performed. Describing in more detail the present process, the via hole 145 corresponding to the bump 130 on the insulating layer 140 is machined by using the YAG laser, the CO2 laser, or the like (see FIG. 8). Thereafter, the circuit layer 150 including the via 155 is formed by the plating process such as a semi-additive process (SAP), a modified semi-additive process (MSAP), a subtractive process, or the like (see FIG. 9A). In this case, in order to protect the circuit layer 150, the solder resist layer 170 may be applied to the exposed surface of the circuit layer 150 and in order to be electrically connected to the external devices, the hole 175 may be formed on the solder resist layer 170 by the exposure and developing process.

Meanwhile, as shown in FIG. 9B, a circuit board having a multi-layer structure may be manufactured by disposing a build up layer 160 in which a plurality of circuit patterns 163 and an insulating material 165 are alternately stacked on the insulating layer 140 and applying the solder resist layer 170 to the exposed surface of the build up layer 160.

Next, as shown in FIGS. 10A to 11A, the process of removing the carrier 110 is performed. In this configuration, the carrier 110 may be removed by a chemical etching process or a physical releasing process. After the carrier 110 is removed, when the electroless plating layer 120 remains on the insulating layer 140 including the exposed bump 130 (see FIG. 10A), the bump 130 may be conducted to each other. Therefore, the remaining electroless plating layer 120 may be completely removed by the soft etching, or the like (see FIG. 11A). In the present process, when the carrier 110 is removed, one end of the bump 130 is sharply protruded from the insulating layer 140 in a ‘V’-letter shape and the other end thereof is embedded in the insulating layer 140 to be connected to the via 155. One end of the bump 130 is sharp and thus, may be precisely matched with the external devices. Further, the other end of the bump 130 is embedded in the insulating layer 140 so as to be connected to the via 155, such that it is possible to prevent the bump 130 from being destructed and warped due to the external force. In addition, the insulating layer 140 is disposed at the outermost side of the circuit board 100 so as to serve as the solder resist layer. During the above-mentioned process, one end of the bump 130 is protruded from the insulating layer 140. Therefore, unlike the solder resist layer according to the prior art, there is no need to perform the exposure and developing process on the insulating layer 140 so as to expose the bump 130. In addition, since the is no need to form the separate solder resist layer after removing the carrier 110, the warpage of the circuit board that may be caused during the process of forming the solder resist layer may be previously prevented.

Meanwhile, as shown in FIGS. 10B to 11B, even when the build up layer 160 is formed on the insulating layer 140, the circuit board 100 having the multi-layer structure may be manufactured by performing the same process of removing the electroless plating layer 120 remaining after the carrier 110 is removed.

The method of manufacturing a circuit board according to the preferred embodiment of the present invention mainly describes the printed circuit board, but is not necessarily limited thereto. As a result, the method of manufacturing a circuit board may be similarly applied to the semiconductor chip. As a result, when the circuit board 100 is the semiconductor chip, the insulating layer 140 may use ceramics.

As set forth above, the preferred embodiment of the present invention can remove the process of forming separate solder balls by forming the cavities for the bumps in the carriers to form the bumps, thereby simplifying the process of manufacturing a circuit board and reducing the lead time.

In addition, the preferred embodiment of the present invention can embed the bumps in the insulating layer while connecting to the vias through the plating process, thereby increasing the bonding strength between the bump and the circuit board body. Therefore, the preferred embodiment of the present invention can prevent the bumps from being destructed or warped due to the external force.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, they are for specifically explaining the present invention and thus the method of manufacturing a circuit board according to the present invention is not limited thereto, but those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Accordingly, such modifications, additions and substitutions should also be understood to fall within the scope of the present invention. 

1. A method of manufacturing a circuit board, comprising: (A) forming a cavity for a bump on one surface of a carrier; (B) forming a bump in the cavity for the bump through an electroplating process; (C) laminating an insulating layer on one surface of the carrier so as to apply the bump; (D) forming a circuit layer including a via connected with the bump on the insulating layer; and (E) removing the carrier.
 2. The method as set forth in claim 1, wherein at the forming of the cavity for the bump, the cavity for the bump has a width narrowing in a direction towards the other surface of the carrier.
 3. The method as set forth in claim 1, wherein at the forming of the bump, the bump is protruded from one surface of the carrier.
 4. The method as set forth in claim 1, wherein at the forming of the cavity for the bump, the carrier is made of metal.
 5. The method as set forth in claim 1, further comprising forming an electroless plating layer on one surface of the carrier by an electroless plating process prior to the forming of the bump.
 6. The method as set forth in claim 5, further comprising removing the electroless plating layer remaining on the insulating layer including the exposed bump after the removing of the carrier.
 7. The method as set forth in claim 1, wherein at the forming of the bump, one surface of the carrier is provided with a terminal for a passive device, a stiffener, a heat radiation layer, or an electromagnetic wave shield layer by the electroplating process.
 8. The method as set forth in claim 7, wherein at the stacking of the insulating layer, the terminal for the passive device, the stiffener, the heat radiation layer, or the electromagnetic wave shield layer are embedded in the insulating layer.
 9. The method as set forth in claim 1, wherein at the stacking of the insulating layer, the insulating layer is a thermosetting insulating layer.
 10. The method as set forth in claim 1, further comprising forming a build up layer on the insulating layer after the forming of the circuit layer on the insulating layer. 